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SH7750_08 Datasheet, PDF (725/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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Section 14 Direct Memory Access Controller (DMAC)
DMA destination address registers 0â7 (DAR0âDAR7) are 32-bit readable/writable registers that
specify the destination address for a DMA transfer. The functions of these registers are the same
as on the SH7750 and SH7750S. For more information, see section 14.2.2, DMA Destination
Address Registers 0â3 (DAR0âDAR3).
14.7.3 DMA Transfer Count Registers 0â7 (DMATCR0âDMATCR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 â â â â â â â â
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: â â â â â â â â â â â â â â â â
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA transfer count registers 0â7 (DMATCR0âDMATCR7) are 32-bit readable/writable registers
that specify the number of transfers in transfer operations for the corresponding channel (byte
count, word count, longword count, quadword count, or 32-byte count). Functions of these
registers are the same as the transfer-count registers of the SH7750 or SH7750S. For more
information, see section 14.2.3, DMA Transfer Count Registers 0â3 (DMATCR0âDMATCR3).
14.7.4 DMA Channel Control Registers 0â7 (CHCR0âCHCR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC â â â â DS RL AM AL
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W (R/W) R/W (R/W)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TM TS2 TS1 TS0 QCL IE TE DE
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/(W) R/W
Rev.7.00 Oct. 10, 2008 Page 641 of 1074
REJ09B0366-0700
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