SH7750_08 Datasheet, PDF (804/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Serial Communication Interface (SCI)
Handling of TEND Flag and TE Bit: The TEND flag is set to 1 when the stop bit of the final
data segment is transmitted. If the TE bit is cleared immediately after confirming that the TEND
flag was set, transmission may not complete properly because stop bit transmission processing is
still underway. Therefore, wait at least 0.5 serial clock cycles (1.5 cycles if two stop bits are used)
after confirming that the TEND flag was set before clearing the TE bit.
Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission
cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE
flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission.
Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: The SCI
operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure
15.24.
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
Base clock
–7.5 clocks
+7.5 clocks
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode
Rev.7.00 Oct. 10, 2008 Page 720 of 1074
REJ09B0366-0700