SH7750_08 Datasheet, PDF (287/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Floating-Point Unit (FPU)
Table 6.3 Incorrect Operation Result
Input
Problem Type Instruction
DRm
DRn
(1)
FDIV
+0/–0
(A) DENORM
(2)
FDIV
(A) DENORM
+0/–0
(A) DENORM (A) DENORM
(3)
FDIV
(A) DENORM +INF/–INF
(4)
FDIV
(C) qNaN (A) DENORM
(C) qNaN (B) DENORM
(B) DENORM (C) qNaN
(5)
FADD/FSUB (C) qNaN
DENORM
DENORM
(C) qNaN
(6)
FMUL
(C) qNaN (B) DENORM
(B) DENORM (C) qNaN
(7)
FMUL
(A) DENORM +INF/–INF
+INF/–INF (A) DENORM
Note: * qNaN: H'7FF7FFFF_FFFFFFFF
SH-4
+0/–0
+0/–0
+INF/–INF
FPU Error
FPU Error
FPU Error
+INF/–INF
Expected
Value
DZ
FPU Error
FPU Error
qNaN^*
qNaN^*
qNaN^*
FPU Error
The above operations complete normally when FPSCR.DN = 1.
Rev.7.00 Oct. 10, 2008 Page 203 of 1074
REJ09B0366-0700