SH7750_08 Datasheet, PDF (1060/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
CKIO
BANK
TRs1
TRs2
TRs3
TRs4
t_AD
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(write)
BS
CKE
DACKn
t_CSD
t_CSD
t_CSD
t_RWD
t_RASD
t_RASD
t_RASD
t_CASD2
t_CASD2
t_CASD2
t_DQMD
t_WDD
t_CKED
t_DACD
TRs5
Trc
Trc
Trc
t_AD
t_RWD
t_CASD2
t_BSD
t_CKED
t_CSD
t_RASD
t_DQMD
t_WDD
t_DACD
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh
(TRC[2:0] = 001)
Rev.7.00 Oct. 10, 2008 Page 976 of 1074
REJ09B0366-0700