SH7750_08 Datasheet, PDF (634/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Table 14.2 DMAC Pins in DDT Mode
Pin Name
Data bus request
Data bus available
Abbreviation
DBREQ
(DREQ0)
BAVL
(DRAK0)
Transfer request signal TR
(DREQ1)
DMAC strobe
Channel number
notification
TDACK
(DACK0)
ID [1:0]
(DRAK1, DACK1)
I/O
Input
Output
Input
Output
Output
Function
Data bus release request from external
device for DTR format input
Data bus release notification
Data bus can be used 2 cycles after
BAVL is asserted
If asserted 2 cycles after BAVL
assertion, DTR format is sent
Only TR asserted: DMA request
DBREQ and TR asserted
simultaneously: Direct request to
channel 2
Reply strobe signal for external device
from DMAC
Notification of channel number to
external device at same time as TDACK
output
(ID [1] = DRAK1, ID [0] = DACK1)
14.1.4 Register Configuration (SH7750, SH7750S)
Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers
are allocated to each channel, and an additional control register is shared by all four channels.
Table 14.3 DMAC Registers
Chan-
nel Name
0
DMA source
address register 0
DMA destination
address register 0
DMA transfer
count register 0
DMA channel
control register 0
Abbre-
viation
SAR0
Read/
Write
R/W^*2
Area 7
Initial Value P4 Address Address
Access
Size
Undefined H'FFA00000 H'1FA00000 32
DAR0
R/W^*2 Undefined H'FFA00004 H'1FA00004 32
DMATCR0 R/W^*2 Undefined H'FFA00008 H'1FA00008 32
CHCR0 R/W^{*1 *2} H'00000000 H'FFA0000C H'1FA0000C 32
Rev.7.00 Oct. 10, 2008 Page 550 of 1074
REJ09B0366-0700