SH7750_08 Datasheet, PDF (529/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
When software wait insertion is specified by WCR2, the external wait input RDY signal is also
sampled. RDY signal sampling is shown in figure 13.12. A single-cycle wait is specified as a
software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore,
the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle. The RDY signal is
sampled on the rising edge of the clock.
CKIO
A25–A0
CSn
RD/WR
RD
(read)
D63–D0
(read)
WEn
(write)
D63–D0
(write)
BS
T1
Tw
Twe
T2
RDY
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)
Rev.7.00 Oct. 10, 2008 Page 445 of 1074
REJ09B0366-0700