SH7750_08 Datasheet, PDF (552/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM
Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0)
LSI Address Pin
Synchronous DRAM Address Pin
RAS Cycle CAS Cycle
Function
A14
A22
A22
A11
BANK select bank address
A13
A21
H/L
A10
Address precharge setting
A12
A20
0
A9
A11
A19
0
A8
A10
A18
A10
A7
A9
A17
A9
A6
A8
A16
A8
A5
A7
A15
A7
A4
A6
A14
A6
A3
A5
A13
A5
A2
A4
A12
A4
A1
A3
A11
A3
A0
A2
—
A2
Not used
A1
—
A1
Not used
A0
—
A0
Not used
Burst Read: The timing chart for a burst read is shown in figure 13.28. In the following example
it is assumed that four 512K × 16-bit × 2-bank synchronous DRAMs are connected, and a 64-bit
data width is used. The burst length is 4. Following the Tr cycle in which ACTV command output
is performed, a READA command is issued in the Tc1 cycle, and the read data is accepted on the
rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is
used to wait for completion of auto-precharge based on the READA command inside the
synchronous DRAM; no new access command can be issued to the same bank during this cycle. In
this LSI, the number of Tpc cycles is determined by the specification of bits TPC2–TPC0 in MCR,
and commands are not issued for synchronous DRAM during this interval.
The example in figure 13.28 shows the basic cycle. To connect slower synchronous DRAM, the
cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READA command output cycle, Tc1, can be specified by bits
RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case
of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous
DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READA
Rev.7.00 Oct. 10, 2008 Page 468 of 1074
REJ09B0366-0700