SH7750_08 Datasheet, PDF (959/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 User Break Controller (UBC)
Conditions set: Independent channel A/channel B mode
⎯ Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00
Bus cycle: CPU, instruction access (pre-instruction-execution), write, word
⎯ Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00
Data: H'00000000 / data mask: H'00000000
Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not
included in conditions)
A user break interrupt is not generated on channel A since the instruction access is not a write
cycle.
A user break interrupt is not generated on channel B since instruction access is performed on
an even address.
Operand Access Cycle Break Condition Settings
• Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 /
BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 /
BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080
Conditions set: Independent channel A/channel B mode
⎯ Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00
Bus cycle: operand access, read (operand size not included in conditions)
⎯ Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02
Data: H'0000A512 / data mask: H'00000000
Bus cycle: operand access, write, word
Data break enabled
On channel A, a user break interrupt is generated in the event of a longword read at address
H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with
ASID = H'80.
On channel B, a user break interrupt is generated when H'A512 is written by word access to
any address from H'000AB000 to H'000ABFFE with ASID = H'70.
Rev.7.00 Oct. 10, 2008 Page 875 of 1074
REJ09B0366-0700