SH7750_08 Datasheet, PDF (288/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Floating-Point Unit (FPU)
Special cases involving double-precision FDIV, FADD, FSUB, and FMUL instructions are
summarized below.
: Shaded portion indicates normal operation.
: Unshaded portion indicates incorrect operation result, and FPU output values are listed
Table 6.4 FDIV DRm, DRn (DRn/DRm → DRn)
DRn
DRm
NORM
+0
−0
+INF
−INF
NORM +0
(A)
(A)
Positive Negative (B)
−0 +INF −INF DENORM DENORM DENORM
DIV 0
INF
Error
DZ Invalid
+INF INF +0 (1)
−0 (1)
DZ
INF +INF −0 (1)
+0 (1)
0
+0 −0 Invalid
Error
−0 +0
(C)
qNaN
qNaN
(D)
qNaN sNaN
Invalid
(A) Positive
DENORM
+0 (2) −0 (2)
(3)
+INF
(3)
−INF
+0 (2)
−0 (2)
(A) Negative
DENORM
(B) DENORM
(C) qNaN
(D) qNaN
sNaN
−0 (2) +0 (2)
(3)
−INF
(3)
+INF
−0 (2)
+0 (2)
Error
(4)
Error (4)
Rev.7.00 Oct. 10, 2008 Page 204 of 1074
REJ09B0366-0700