SH7750_08 Datasheet, PDF (855/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number
can be read from SCFRDR2, allowing efficient continuous reception.
However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number,
the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after
being read as 1 after all the receive data has been read.
The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO
data count register (SCFDR2).
Break Detection and Processing: Break signals can be detected by reading the RxD2 pin directly
when a framing error (FER) is detected. In the break state the input from the RxD2 pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Although the SCIF stops transferring receive data to SCFRDR2 after receiving a break, the receive
operation continues.
Sending a Break Signal: The input/output condition and level of the TxD2 pin are determined by
bits SPB2IO and SPB2DT in the serial port register (SCSPTR2). This feature can be used to send
a break signal.
After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the
SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled).
The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level)
beforehand.
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized, regardless of its current state, and 0 is output from the TxD2 pin.
Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a
frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall
of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the
eighth base clock pulse. The timing is shown in figure 16.13.
Rev.7.00 Oct. 10, 2008 Page 771 of 1074
REJ09B0366-0700