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| SH7750_08 Datasheet, PDF (553/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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Section 13 Bus State Controller (BSC)
command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles
independently for areas 2 and 3 by means of bits A2W2âA2W0 and A3W2âA3W0 in WCR2. This
number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
CKIO
Bank
Precharge-sel
Tr
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td2
Td3
Td4
Row
Row
H/L
Address
Row
c0
CSn
RD/WR
RAS
CASS
DQMn
D63âD0
(read)
d0
d1
d2
d3
BS
CKE
DACKn
(SA: IO â memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.28 Basic Timing for Synchronous DRAM Burst Read
Rev.7.00 Oct. 10, 2008 Page 469 of 1074
REJ09B0366-0700
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