SH7750_08 Datasheet, PDF (277/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Floating-Point Unit (FPU)
6.4 Rounding
In a floating-point instruction, rounding is performed when generating the final operation result
from the intermediate result. Therefore, the result of combination instructions such as FMAC,
FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB,
or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL.
There are two rounding methods, the method to be used being determined by the RM field in
FPSCR.
• RM = 00: Round to Nearest
• RM = 01: Round to Zero
Round to Nearest: The value is rounded to the nearest expressible value. If there are two nearest
expressible values, the one with an LSB of 0 is selected.
If the unrounded value is 2^Emax (2 – 2^–P) or more, the result will be infinity with the same sign as the
unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and
1023 and 53 for double-precision.
Round to Zero: The digits below the round bit of the unrounded value are discarded.
If the unrounded value is larger than the maximum expressible absolute value, the value will be
the maximum expressible absolute value.
6.5 Floating-Point Exceptions
FPU-related exceptions are as follows:
• General illegal instruction/slot illegal instruction exception
The exception occurs if an FPU instruction is executed when SR.FD = 1.
• FPU exceptions
The exception sources are as follows:
⎯ FPU error (E): When FPSCR.DN = 0 and a denormalized number is input
⎯ Invalid operation (V): In case of an invalid operation, such as NaN input
⎯ Division by zero (Z): Division with a zero divisor
⎯ Overflow (O): When the operation result overflows
⎯ Underflow (U): When the operation result underflows
⎯ Inexact exception (I): When overflow, underflow, or rounding occurs
Rev.7.00 Oct. 10, 2008 Page 193 of 1074
REJ09B0366-0700