SH7750_08 Datasheet, PDF (350/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Power-Down Modes
Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
Description
0
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
1
Transition to deep sleep mode on execution of SLEEP instruction*
Note: * When the STBY bit in the STBCR register is 0
Bit 6—STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0
and STATUS1 pins are set to high-impedance when in hardware standby mode.
Bit 6: STHZ
0
1
Description
Sets STATUS0, 1 pins to high-impedance when in hardware standby mode
(Initial value)
Drives STATUS0, 1 pins to LH when in hardware standby mode
Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Bits 1 and 0 (SH7750)—Reserved: Only 0 should only be written to these bits; operation cannot
be guaranteed if 1 is written. These bits are always read as 0.
Bit 1 (SH7750S and SH7750R)—Module Stop 6 (MSTP6): Specifies that the clock supply to
the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops
the clock supply to the SQ, and the SQ functions are therefore unavailable.
Bit 1: MSTP6
0
1
Description
SQ operating
Clock supply to SQ stopped
(Initial value)
Bit 0 (SH7750S and SH7750R)—Module Stop 5 (MSTP5): Specifies stopping of the clock
supply to the user break controller (UBC) among the on-chip peripheral modules. See section
20.6, User Break Controller Stop Function, for how to set the clock supply.
Bit 0: MSTP5
0
1
Description
UBC operating
Clock supply to UBC stopped
(Initial value)
Rev.7.00 Oct. 10, 2008 Page 266 of 1074
REJ09B0366-0700