SH7750_08 Datasheet, PDF (805/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Serial Communication Interface (SCI)
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 – ¹ ) – (L – 0.5) F – ^{| D – 0.5 |} (1 + F) × 100% ^{................ (1)}
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ............................................ (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
When Using the DMAC:
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC.
Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is
updated. (See figure 15.25)
SCK
t
TDRE
TxD
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t > 4.
Figure 15.25 Example of Synchronous Transmission by DMAC
• When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI)
as the activation source with bits RS3 to RS0 in CHCR.
Rev.7.00 Oct. 10, 2008 Page 721 of 1074
REJ09B0366-0700