SH7750_08 Datasheet, PDF (20/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
13.3.5 Synchronous 466
DRAM Interface
Figure 13.26 Example
of 64-Bit Data Width
Synchronous DRAM
Connection (Area 3)
Figure 13.27 Example 467
of 32-Bit Data Width
Synchronous DRAM
Connection (Area 3)
Figure 13.37 Burst 481
Write Timing (Different
Row Addresses)
Power-On Sequence: 490
Figure 13.42 (1)
Synchronous DRAM
Mode Write Timing
(PALL)
Revision (See Manual for Details)
Figure amended
SH7750, SH7750S, SH7750R
A12–A3
CKIO
CKE
CS3
RAS
CASS
RD/WR
D63–D48
DQM7
DQM6
Figure amended
SH7750, SH7750S, SH7750R
A11–A2
CKIO
CKE
CS3
RAS
CASS
RD/WR
D31–D16
DQM3
DQM2
Figure amended
CKIO
Tpr Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Trwl
Bank
Row
Row
Precharge-sel
H/L
Row
H/L
Address
CSn
RD/WR
Row
c1
Figure amended
CASS
D63–D0
CKE
(High)
Rev.7.00 Oct. 10, 2008 Page xx of lxxxiv
REJ09B0366-0700