SH7750_08 Datasheet, PDF (66/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 13.6 Basic Timing of SRAM Interface........................................................................... 439
Figure 13.7 Example of 64-Bit Data Width SRAM Connection ............................................... 440
Figure 13.8 Example of 32-Bit Data Width SRAM Connection ............................................... 441
Figure 13.9 Example of 16-Bit Data Width SRAM Connection ............................................... 442
Figure 13.10 Example of 8-Bit Data Width SRAM Connection ................................................. 443
Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) ............................................ 444
Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal) .......... 445
Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) ...... 446
Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3) ............................... 448
Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) ............................... 449
Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) .................... 450
Figure 13.17 Basic DRAM Access Timing ................................................................................. 452
Figure 13.18 DRAM Wait State Timing ..................................................................................... 453
Figure 13.19 DRAM Burst Access Timing ................................................................................. 454
Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)............................ 455
Figure 13.21 Burst Access Timing in DRAM EDO Mode.......................................................... 456
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0) .......................................................... 457
Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, AnW = 0) .......................................................... 458
Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start
(EDO Mode, RCD = 0, AnW = 0).................................................................. 459
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0).................................................................. 460
Figure 13.23 CAS-Before-RAS Refresh Operation..................................................................... 461
Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1).............. 462
Figure 13.25 DRAM Self-Refresh Cycle Timing........................................................................ 464
Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) .......... 466
Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .......... 467
Figure 13.28 Basic Timing for Synchronous DRAM Burst Read ............................................... 469
Figure 13.29 Basic Timing for Synchronous DRAM Single Read.............................................. 471
Figure 13.30 Basic Timing for Synchronous DRAM Burst Write .............................................. 473
Figure 13.31 Basic Timing for Synchronous DRAM Single Write............................................. 474
Figure 13.32 Burst Read Timing ................................................................................................. 476
Figure 13.33 Burst Read Timing (RAS Down, Same Row Address).......................................... 477
Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)................................. 478
Figure 13.35 Burst Write Timing ................................................................................................ 479
Figure 13.36 Burst Write Timing (Same Row Address) ............................................................. 480
Figure 13.37 Burst Write Timing (Different Row Addresses) .................................................... 481
Rev.7.00 Oct. 10, 2008 Page lxvi of lxxxiv
REJ09B0366-0700