SH7750_08 Datasheet, PDF (474/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
• Idle Insertion between Accesses
Following Cycle
Same Area
Different Area
Same
Area
Different
Area
Preceding
Cycle
Read
CPU DMA
Write
CPU DMA
Read
CPU DMA
Write
CPU DMA
MPX
MPX
Address Address
Output Output
Read
MM
MM
MM
M (1)
M (1)
Write
MM
MM
*²
M
DMA read
(memory →
device)
MM
MM
MM
—
M (1)
DMA write D D
D
D^*1
D
D
DD
—
(device →
memory)
D (1)
“DMA” in the table indicates DMA single-address transfer. DMA dual transfer is in accordance with
the CPU.
Legend:
M, D: Idle wait always inserted by WCR1
(M(1): One cycle inserted in MPX access even if WCR1 is cleared to 0)
M: Idle cycles according to setting of AnIW2-AnIW0 (area 0 to area 6)
D: Idle cycles according to setting of DMAIW2-DMAIW0
Notes: When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to 000
and bits A3IW2-A3IW0 to 000.
1. Inserted when device is switched
2. On the MPX interface, a WCR1 idle wait may be inserted before an access (either read
or write) to the same area after a write access. The specific conditions for idle wait
insertion in accesses to the same area are shown below.
(a) Synchronous DRAM set to RAS down mode
(b) Synchronous DRAM accessed by on-chip DMAC
Apart from use under above conditions (a) and (b), an idle wait is also inserted between
an MPX interface write access and a following access to the same area. Even under
the above conditions, an idle wait may be inserted in a same-area access following an
interface write access, depending on the synchronous DRAM pipeline access situation.
An idle wait is not inserted when the WCR1 register setting is 0. The setting for the
number of idle state cycles inserted after a power-on reset is the default value of 15 (the
maximum value), so ensure that the optimum value is set.
Rev.7.00 Oct. 10, 2008 Page 390 of 1074
REJ09B0366-0700