SH7750_08 Datasheet, PDF (322/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
8.2 Parallel-Executability
Instructions are categorized into six groups according to the internal function blocks used, as
shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of
groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel.
Table 8.1 Instruction Groups
1. MT Group
CLRT
CMP/EQ
CMP/EQ
CMP/GE
CMP/GT
#imm,R0
Rm,Rn
Rm,Rn
Rm,Rn
CMP/HI
CMP/HS
CMP/PL
CMP/PZ
CMP/STR
Rm,Rn
Rm,Rn
Rn
Rn
Rm,Rn
MOV
NOP
SETT
TST
TST
Rm,Rn
#imm,R0
Rm,Rn
2. EX Group
ADD
ADD
ADDC
ADDV
AND
AND
DIV0S
DIV0U
DIV1
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MOV
MOVA
#imm,Rn
MOVT
Rm,Rn
NEG
Rm,Rn
NEGC
Rm,Rn
NOT
#imm,R0
OR
Rm,Rn
OR
Rm,Rn
ROTCL
ROTCR
Rm,Rn
ROTL
Rn
ROTR
Rm,Rn
SHAD
Rm,Rn
SHAL
Rm,Rn
SHAR
Rm,Rn
SHLD
#imm,Rn
SHLL
@(disp,PC),R0 SHLL16
Rn
Rm,Rn
Rm,Rn
Rm,Rn
#imm,R0
Rm,Rn
Rn
Rn
Rn
Rn
Rm,Rn
Rn
Rn
Rm,Rn
Rn
Rn
SHLL2
SHLL8
SHLR
SHLR16
SHLR2
SHLR8
SUB
SUBC
SUBV
SWAP.B
SWAP.W
XOR
XOR
XTRCT
Rn
Rn
Rn
Rn
Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
#imm,R0
Rm,Rn
Rm,Rn
Rev.7.00 Oct. 10, 2008 Page 238 of 1074
REJ09B0366-0700