SH7750_08 Datasheet, PDF (262/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
5.6.3 Interrupts
(1) NMI
• Source: NMI pin edge detection
• Transition address: VBR + H'0000 0600
• Transition operations:
The contents of PC and SR immediately after the instruction at which this interrupt was
accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not
masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the
BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or
accepted. For details, see section 19, Interrupt Controller (INTC).
NMI()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'000001C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000600;
}
Rev.7.00 Oct. 10, 2008 Page 178 of 1074
REJ09B0366-0700