SH7750_08 Datasheet, PDF (1040/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
CKIO
A25–A0
CSn
RD/WR
RD
D63–D0
(read)
WEn
D63–D0
(write)
BS
T1
T2
t_AD
t_CSD
t_RWD
t_AD
t_CSD
t_RWD
t_RSD
t_RSD
t_RSD
t_RDS
t_RDH
t_{WED1 tWEDF}
t_WEDF
t_WDD
t_WDD
t_WDD
t_BSD
t_BSD
RDY
DACKn
(SA: IO ← memory)
t_DACD
t_DACD
t_DACD
DACKn
(SA: IO → memory)
t_DACDF
t_DACDF
DACKn
(DA)
t_DACD
t_DACD
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
Rev.7.00 Oct. 10, 2008 Page 956 of 1074
REJ09B0366-0700