SH7750_08 Datasheet, PDF (721/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Table 14.12 DMAC Pins in DDT Mode
Pin Name
Data bus request
Data bus available
Abbreviation
DBREQ
(DREQ0)
BAVL/ID2
(DRAK0)
Transfer request signal TR
(DREQ1)
DMAC strobe
Channel number
notification
TDACK
(DACK0)
ID[1:0]
(DRAK1, DACK1)
I/O
Input
Output
Input
Output
Output
Function
Data bus release request from external
device for DTR format input
Data bus release notification
Data bus can be used 2 cycles after
BAVL is asserted
Notification of channel number to
external device at same time as TDACK
output
If asserted 2 cycles after BAVL
assertion, DTR format is sent
Only TR asserted: DMA request
DBREQ and TR asserted
simultaneously: Direct request to
channel 2
Reply strobe signal for external device
from DMAC
Notification of channel number to
external device at same time as TDACK
output
(ID [1] = DRAK1, ID [0] = DACK1)
Requests for DMA transfer from external devices are normally accepted only on channel 0
(DREQ0) and channel 1 (DREQ1). In DDT mode, the BAVL pin functions as both the data-bus-
available pin and channel-number-notification (ID2) pin.
14.6.3 Register Configuration (SH7750R)
Table 14.13 shows the configuration of the DMAC's registers. The DMAC of the SH7750R has a
total of 33 registers: four registers are assigned to each channel, and there is a control register for
the overall control of the DMAC.
Rev.7.00 Oct. 10, 2008 Page 637 of 1074
REJ09B0366-0700