SH7750_08 Datasheet, PDF (724/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
2. In the SH7750R, writes from the CPU and writes from external I/O devices using the
DTR format are possible in DDT mode.
14.7 Register Descriptions (SH7750R)
14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA source address registers 0−7 (SAR0−SAR7) are 32-bit readable/writable registers that
specify the source address for a DMA transfer. The functions of these registers are the same as on
the SH7750 or SH7750S. For more information, see section 14.2.1, DMA Source Address
Registers 0−3 (SAR0−SAR3).
14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.7.00 Oct. 10, 2008 Page 640 of 1074
REJ09B0366-0700