SH7750_08 Datasheet, PDF (1111/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix C Mode Pin Settings
Appendix C Mode Pin Settings
The MD8–MD0 pin values are input in the event of a power-on reset via the RESET or
SCK2/MRESET pin.
(1) Clock Modes
• Clock Operating Modes (SH7750, SH7750S)
External
Pin Combination
Frequency
(vs. Input Clock)
Clock
1/2
Peripheral FRQCR
Operating
Frequency
CPU Bus Module Initial
Mode
MD2 MD1 MD0 Divider PLL1 PLL2 Clock Clock Clock
Value
0
0 0 0 Off
On On 6
3/2 3/2
H'0E1A
1
1 Off
On On 6
1
1
H'0E23
2
1 0 On
On On 3
1
1/2
H'0E13
3
1 Off
On On 6
2
1
H'0E13
4
1 0 0 On
On On 3
3/2 3/4
H'0E0A
5
1 Off
On On 6
3
3/2
H'0E0A
Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating
mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f_EX) and CKIO clock output (f_OP) in section 22.3.1, Clock and Control Signal
Timing.
Rev.7.00 Oct. 10, 2008 Page 1027 of 1074
REJ09B0366-0700