SH7750_08 Datasheet, PDF (25/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
14.5.2 Pins in DDT 605
Mode
Figure 14.24 System
Configuration in On-
Demand Data Transfer
Mode
Revision (See Manual for Details)
Figure amended
SH7750, SH7750S, SH7750R
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D63–D0=DTR
External device
• TR: Transfer request
signal
608
14.8.3 Transfer
648
Channel Notification in
DDT Mode
Table 14.16 Function
of BAVL
14.9 Usage Notes 653
10. [SH7750 Only]
15.1 Overview
655
A25–A0, RAS, CAS, WE, DQMn, CKE
Synchronous
DRAM
Description amended
Assertion of TR has the following different meanings.
⎯ In normal data transfer mode (channel 0, except channel 0),
TR is asserted, and at the same time the DTR format is
output, two cycles after BAVL is asserted.
Notes amended
7. For DTR format transfer when ID[1:0] = 00, input MD[1:0]
and SZ ≠ 101, 110.
Description amended
When the DMAC is set up for eight-channel external request
acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits
and the simultaneous (on the timing of TDACK assertion)
assertion of ID2 from the BAVL (data bus available) pin are
used to notify the external device of the DMAC channel that is
to be used (see table 14.15).
Table amended
TDACK = High
Function of BAVL
Bus available
Newly added
Description amended
The SCI supports a smart card interface. This is a serial
communication function supporting a subset of the ISO/IEC
7816-3 (identification cards) standard. For details, see section
17, Smart Card Interface.
Rev.7.00 Oct. 10, 2008 Page xxv of lxxxiv
REJ09B0366-0700