SH7750_08 Datasheet, PDF (282/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Floating-Point Unit (FPU)
a. According to IEEE754 standard
Operation result: H'00800000
FPSCR: H'0004300C
b. FPU
Operation result: H'00800000
FPSCR: H'00041004
• Double-precision
When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 1 (double-precision), and the
FDIV instruction (H'001FFFFF FFFFFFFF / H'40000000 00000000) is executed.
a. According to IEEE754 standard
Operation result: H'00100000 00000000
FPSCR: H'000C300C
b. FPU
Operation result: H'00100000 00000000
FPSCR: H'000C1004
Workarounds
1. Use FPSCR.RM = 01, that is to say Round to Zero rather than Round to Nearest mode.
2. Use FPSCR.RM = 00, that is to say Round to Nearest mode, and set the enable field to 1 to
enable generation of inexact exceptions so that the exception handling routine can be used to
check whether or not an underflow has occurred.
6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction
When the maximum error produced by the FIPR or FTRV instruction exceeds the maximum value
expressible as a normalized number (H'7F7FFFFF), the overflow flag may be set, even through
the operation result is a positive or negative zero (H'00000000 or H'80000000).
Example: The operation result (FR7) after executing the instruction FIPR FV4, FV0 is
H'00000000 (positive zero), but the overflow flag may be set nevertheless.
FPSCR = H'00040001
FR0 = H'FF7EF631 , FR1 = H80000000 , FR2 = H'8087F451 , FR3 = H'7F7EF631
FR4 = H'7F7EF631 , FR5 = H'0087F451 , FR6 = H'7F7EF631 , FR7 = H'7F7EF631
Workaround: Avoid using the FIPR and FTRV instructions, and use the FADD, FMUL, and
FMAC instructions instead.
Rev.7.00 Oct. 10, 2008 Page 198 of 1074
REJ09B0366-0700