SH7750_08 Datasheet, PDF (551/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R
A11–A2
CKIO
CKE
CS3
RAS
CASS
RD/WR
D31–D16
DQM3
DQM2
512K × 16-bit × 2-bank
synchronous DRAM
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
D15–D0
DQM1
DQM0
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2–
AMX0 in MCR. Table 13.16 shows the relationship between the address multiplex specification
bits and the bits output at the address pins. See Appendix F, Synchronous DRAM Address
Multiplexing Tables.
Address pin output at A25–A18, A1, and A0 are undefined.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, with a 32-bit bus
width it makes a longword address specification. Connection should therefore be made in this
order: connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin
A3.
With a 64-bit bus width, the LSB makes a quadword address specification. Connection should
therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A3 of this LSI,
then connect pin A1 to pin A4.
Rev.7.00 Oct. 10, 2008 Page 467 of 1074
REJ09B0366-0700