SH7750_08 Datasheet, PDF (563/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Section 13 Bus State Controller (BSC)
Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl
Row
Row
H/L
Row
c1
D63–D0
(read)
BS
CKE
c1
c2
c3
c4
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.35 Burst Write Timing
Rev.7.00 Oct. 10, 2008 Page 479 of 1074
REJ09B0366-0700