SH7750_08 Datasheet, PDF (931/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19.6 Usage Notes
Section 19 Interrupt Controller (INTC)
19.6.1 NMI Interrupts (SH7750 and SH7750S Only)
When multiple NMI interrupts are input to the NMI pin within a set period of time (which is
dependent on the internal state of the CPU and the external bus state), subsequent interrupts may
not be accepted.
Note that this problem does not occur when sufficient time*¹ is provided between NMI interrupt
inputs or with non-NMI interrupts such as IRL interrupts.
Workarounds: Methods 1, 2, or 3 below may be used to avoid the above problem.
1. Allow sufficient time between NMI interrupt inputs, as described in note 1, below.
Note that it may not be possible to assure the above interval between NMI interrupt inputs if
hazard is input to NMI, and that this may cause the device to malfunction. Design the external
circuits so that no hazard is input via NMI.*²
2. Do not use NMI interrupts. Use IRL interrupts instead.
3. Workaround using software
The above problem can be avoided by inserting the following lines of code*³*⁴ into the NMI
exception handling routine.
Notes: 1. If SR.BL is cleared to 0 so that one or more instructions may be executed between the
handling of two NMI interrupts.
2. When changing the level of the NMI input, ensure that the high and low durations are
at least 5 CKIO cycles. Also ensure that no noise pulses occur before or after level
changes.
3. If the NMI exception handling routine contains code that changes the value of the
SR.BL bit, the code listed below should be inserted before the point at which the
change is made.
4. Registers R0 to R3 in the code sample can be changed to any general register. Also, the
necessary register save and restore instructions should be inserted before and after the
code listed below, as appropriate.
Rev.7.00 Oct. 10, 2008 Page 847 of 1074
REJ09B0366-0700