SH7750_08 Datasheet, PDF (264/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
(3) Peripheral Module Interrupts
• Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI,
GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is
0 (accepted at instruction boundary).
• Transition address: VBR + H'0000 0600
• Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
The code corresponding to the interrupt source is set in INTEVT. The BL, MD, and RB bits
are set to 1 in SR, and a branch is made to VBR + H'0600. The module interrupt levels should
be set as values between B'0000 and B'1111 in the interrupt priority registers (IPRA–IPRC) in
the interrupt controller. For details, see section 19, Interrupt Controller (INTC).
Module_interruption()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'00000400 ~ H'00000B80;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000600;
}
Rev.7.00 Oct. 10, 2008 Page 180 of 1074
REJ09B0366-0700