SH7750_08 Datasheet, PDF (383/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 Clock Oscillation Circuits
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2
oscillation stabilization time is required.
1. Make WDT settings as in section 10.5.1.
2. Set the BFC2–BFC0 bits to the desired value.
3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal
clock stops and an unstable clock is output to the CKIO pin.
4. After the WDT count overflows, clock supply begins within the chip and the processor
resumes operation. The WDT stops after overflowing.
10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not
performed.
1. Set the BFC2–BFC0 bits to the desired value.
2. The set clock is switched to immediately.
10.5.5 Changing CPU or Peripheral Module Clock Division Ratio
When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is
not performed.
1. Set the IFC2–IFC0 or PFC2–PFC0 bits to the desired value.
2. The set clock is switched to immediately.
10.6 Output Clock Control
The CKIO pin can be switched between clock output and a fixed level setting by means of the
CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is
pulled up.
Rev.7.00 Oct. 10, 2008 Page 299 of 1074
REJ09B0366-0700