SH7750_08 Datasheet, PDF (489/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the
DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active command is not issued for the
period set by the TRC[2:0]* and TRAS[2:0] bits after an auto-refresh command is issued.
Note: For setting values and the period during which no command is issued, see 22.3.3, Bus
Timing.
Bit 12: TRAS2
0
Bit 11: TRAS1
0
Bit 10: TRAS0
0
RAS/DRAM
Assertion Period
2
1
3
1
0
4
1
5
1
0
0
6
1
7
1
0
8
1
9
Note: TRC (Bits 29 to 27): RAS precharge interval at end of refresh.
Command
Interval after
Synchronous
DRAM Refresh
4 + TRC
(Initial value)
5 + TRC
6 + TRC
7 + TRC
8 + TRC
9 + TRC
10 + TRC
11 + TRC
Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
BE
EDOMODE
8/16/32/64-Bit Transfer
32-Byte Transfer
0
0
Single
Single
1
Setting prohibited
Setting prohibited
1
0
Single/fast page*
Fast page
1
EDO
EDO
Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit
bus.
Rev.7.00 Oct. 10, 2008 Page 405 of 1074
REJ09B0366-0700