SH7750_08 Datasheet, PDF (1085/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
Figure 22.59 Memory Byte Control SRAM Bus Cycles
(1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait)
(3) Basic Read Cycle (One Internal Wait + One External Wait)
Rev.7.00 Oct. 10, 2008 Page 1001 of 1074
REJ09B0366-0700