SH7750_08 Datasheet, PDF (305/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Instruction Set
Table 7.6 Shift Instructions
Instruction
ROTL
Rn
ROTR
Rn
ROTCL
Rn
ROTCR
Rn
SHAD
Rm,Rn
SHAL
SHAR
SHLD
Rn
Rn
Rm,Rn
SHLL
Rn
SHLR
Rn
SHLL2
Rn
SHLR2
Rn
SHLL8
Rn
SHLR8
Rn
SHLL16
Rn
SHLR16 Rn
Operation
Instruction Code
Privileged T Bit
T ← Rn ← MSB
0100nnnn00000100 —
MSB
LSB → Rn → T
0100nnnn00000101 —
LSB
T ← Rn ← T
0100nnnn00100100 —
MSB
T → Rn → T
0100nnnn00100101 —
LSB
When Rn ≥ 0, Rn << Rm → Rn 0100nnnnmmmm1100 —
—
When Rn < 0, Rn >> Rm →
[MSB → Rn]
T ← Rn ← 0
0100nnnn00100000 —
MSB
MSB → Rn → T
0100nnnn00100001 —
LSB
When Rn ≥ 0, Rn << Rm → Rn 0100nnnnmmmm1101 —
—
When Rn < 0, Rn >> Rm →
[0 → Rn]
T ← Rn ← 0
0100nnnn00000000 —
MSB
0 → Rn → T
0100nnnn00000001 —
LSB
Rn << 2 → Rn
0100nnnn00001000 —
—
Rn >> 2 → Rn
0100nnnn00001001 —
—
Rn << 8 → Rn
0100nnnn00011000 —
—
Rn >> 8 → Rn
0100nnnn00011001 —
—
Rn << 16 → Rn
0100nnnn00101000 —
—
Rn >> 16 → Rn
0100nnnn00101001 —
—
Rev.7.00 Oct. 10, 2008 Page 221 of 1074
REJ09B0366-0700