SH7750_08 Datasheet, PDF (560/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 13.34 or 13.37 is executed instead of
that in figure 13.33 or 13.36. In RAS down mode, too, a PALL command is issued before a refresh
cycle or before bus release due to bus arbitration.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4
Row
Row
H/L
Row
c1
c1 c2 c3 c4
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.32 Burst Read Timing
Rev.7.00 Oct. 10, 2008 Page 476 of 1074
REJ09B0366-0700