SH7750_08 Datasheet, PDF (583/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
A25–A5
A4–A0
CSn
RD/WR
RD
D63–D0
(read)
BS
T1 Tw Tw TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2
RDY
DACKn
(SA: IO ← memory)
Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed.
2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.48 Burst ROM Wait Access Timing
Rev.7.00 Oct. 10, 2008 Page 499 of 1074
REJ09B0366-0700