SH7750_08 Datasheet, PDF (922/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Interrupt Controller (INTC)
Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or
detected immediately while the SR.BL bit is set to 1.
Bit 9: NMIB
Description
0
NMI interrupt requests held pending while SR.BL bit is set to 1
(Initial value)
1
NMI interrupt requests detected while SR.BL bit is set to 1
Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information
will be lost, and so must be saved beforehand.
2. This bit is cleared automatically by NMI acceptance.
Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt
request signal to the NMI pin is detected.
Bit 8: NMIE
0
1
Description
Interrupt request detected on falling edge of NMI input
Interrupt request detected on rising edge of NMI input
(Initial value)
Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as level-
encoded interrupt requests or as four independent interrupt requests.
Bit 7: IRLM
0
1
Description
IRL pins used as level-encoded interrupt requests
(Initial value)
IRL pins used as four independent interrupt requests (level-sense IRQ
mode)
Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written
with 0.
Rev.7.00 Oct. 10, 2008 Page 838 of 1074
REJ09B0366-0700