SH7750_08 Datasheet, PDF (355/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Power-Down Modes
9.5.2 Exit from Standby Mode
Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a
reset via the RESET pin.
Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI,
IRL*¹, RTC, or GPIO*² interrupt is detected, the WDT starts counting. After the count overflows,
clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0
pins both go low. Interrupt exception handling is then executed, and the code corresponding to the
interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the
BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack
before executing the SLEEP instruction.
The phase of the CKIO pin clock output may be unstable immediately after an interrupt is
detected, until standby mode is exited.
Notes: 1. Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL
Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3–
IRL0 level is higher than the SR register IMASK mask level).
2. GPIO can be used to cancel standby mode when the RTC clock (32.768 kHz) is
operating (when the GPIO level is higher than the SR register IMASK mask level).
Exit by Reset: Standby mode is exited by means of a reset (power-on or manual) via the RESET
pin. The RESET pin should be held low until clock oscillation stabilizes. The internal clock
continues to be output at the CKIO pin.
9.5.3 Clock Pause Function
In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL
pin. This function is used as follows.
1. Enter standby mode following the transition procedure described above.
2. When standby mode is entered and the chip's internal clock stops, a low-level signal is output
at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
3. The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the
STATUS0 pin high.
4. When the frequency is changed, input an NMI or IRL interrupt after the change. When the
clock is stopped, input an NMI or IRL interrupt after applying the clock.
5. After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and
STATUS0 pins both go low, and operation is resumed from interrupt exception handling.
Rev.7.00 Oct. 10, 2008 Page 271 of 1074
REJ09B0366-0700