SH7750_08 Datasheet, PDF (289/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Floating-Point Unit (FPU)
Table 6.5 FADD DRm, DRn (DRn + DRm → DRn)
FSUB DRm, DRn (DRn − DRm → DRn)
DRn
DRm
NORM +0
NORM
ADD
+0
+0
−0
+INF
−INF
−INF
(A) Positive
DENORM
(A)
(A)
Positive Negative (B)
(C)
−0 +INF −INF DENORM DENORM DENORM qNaN
+INF −INF
Error
(D)
qNaN
sNaN
−0
Invalid
Invalid −INF
qNaN
Error (5)
Invalid
(A) Negative
DENORM
(B) DENORM
(C) qNaN
(D) qNaN
sNaN
Error
(5)
Table 6.6 FMUL DRm, DRn (DRn*DRm → DRn)
DRn
DRm
NORM
+0
−0
+INF
−INF
NORM +0
MUL 0
+0
−0
INF Invalid
(A)
(A)
Positive Negative (B)
−0 +INF −INF DENORM DENORM DENORM
INF
Error
−0 Invalid
+0
+INF −INF +INF (7) −INF (7)
−INF +INF −INF (7) +INF (7)
(C)
qNaN
qNaN
(D)
qNaN sNaN
Invalid
(A) Positive
DENORM
+INF −INF
(7) (7)
(A) Negative
DENORM
−INF +INF
(7) (7)
(B) DENORM
(C) qNaN
(D) qNaN
sNaN
Error (6)
Error (6)
Rev.7.00 Oct. 10, 2008 Page 205 of 1074
REJ09B0366-0700