SH7750_08 Datasheet, PDF (164/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 3 Memory Management Unit (MMU)
In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from
the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always
performed using the values of the SA and TC bits set in the PTEA register.
The PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn,
CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct
Memory Access Controller (DMAC).
P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or
not the cache is used is determined by the cache control register (CCR). When the cache is used,
with the exception of the P1 area, switching between the copy-back method and the write-through
method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified
by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding
external memory space address. However, since area 7 in the external memory space is a reserved
area, a reserved area also appears in these areas.
P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3
bits of an address gives the corresponding external memory space address. However, since area 7
in the external memory space is a reserved area, a reserved area also appears in this area.
P4 Area: The P4 area is mapped onto SH-4 on-chip I/O channels. This area cannot be accessed
using the cache. The P4 area is shown in detail in figure 3.4.
Rev.7.00 Oct. 10, 2008 Page 80 of 1074
REJ09B0366-0700