SH7750_08 Datasheet, PDF (388/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 Clock Oscillation Circuits
Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT
count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow
periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1
off, and PLL circuit 1 on (×6).
Note: * When PLL1 is switched on or off, the clock following the switch is used.
Description
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio
Overflow Period
0
0
0
1/32 (Initial value)
41 μs
1
1/64
82 μs
1
0
1/128
164 μs
1
1/256
328 μs
1
0
0
1/512
656 μs
1
1/1024
1.31 ms
1
0
1/2048
2.62 ms
1
1/4096
5.25 ms
Note: The up-count may not be performed correctly if bits CKS2–CKS0 are modified while the
WDT is running. Always stop the WDT before modifying these bits.
Rev.7.00 Oct. 10, 2008 Page 304 of 1074
REJ09B0366-0700