SH7750_08 Datasheet, PDF(40/1162 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7750_08 Datasheet, PDF (40/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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Item

Page

22.3.3 Bus Timing 973

Figure 22.32

Synchronous DRAM

Normal Write Bus Cycle:

WRITE Command,

Burst (RASD = 1,

TRWL[2:0] = 010)

Figure 22.52 PCMCIA 994

Memory Bus Cycle

(1) TED[2:0] = 000,

TEH[2:0] = 000, No Wait

(2) TED[2:0] = 001,

TEH[2:0] = 001, One

Internal Wait + One

External Wait

22.3.4 Peripheral

1003,

Module Signal Timing 1004

Table 22.34 Peripheral

Module Signal Timing

(1)

Table 22.34 Peripheral 1005,

Module Signal Timing 1006

(2)

Revision (See Manual for Details)

Title amended

Notes amended

Note: *: SH7750S and SH7750R only

Table amended

Module Item

Symbol

HD6417750

RBP240 (V)

HD6417750

RBG240 (V)

*2

Min Max

HD6417750

RBP200 (V)

HD6417750

RBG200 (V)

*2

Min Max

Table and notes amended

Module Item

Symbol

HD6417750S

VF133 (V)

HD6417750S

VBT133 (V)

*2

Min Max

HD6417750

SF167 (V)

HD6417750

SF200 (V)

*3

Min Max

Notes: 1. Pcyc: P clock cycles

2. VDDQ = 3.0 to 3.6 V, VDD =

C = 30 pF, PLL2 on

L

3. VDDQ = 3.0 to 3.6 V, VDD =

CL = 30 pF, PLL2 on

1.5 V, Ta = â20 to +75Â°C,

1.8 V, Ta = â20 to +75Â°C,

4. V = 3.0 to 3.6 V, V = 1.8 V, T = â20 to +75Â°C,

DDQ

DD

a

C = 30 pF, PLL2 on

L

Rev.7.00 Oct. 10, 2008 Page xl of lxxxiv

REJ09B0366-0700

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