SH7750_08 Datasheet, PDF (45/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
E.1 Pin States
1035,
Table E.1 Pin States in ¹⁰³⁶
Reset, Power-Down
State, and Bus-
Released State
Revision (See Manual for Details)
PI: Input (Pulled Up)
PZ: High-impedance (Pulled Up)
Notes: 1. Output when area 2 is used as DRAM.
2. Output when area 5 is used as PCMCIA.
3. Output when area 6 is used as PCMCIA.
4. Z (I) or O on refresh operations, depending on
register setting (BCR1.HIZCNT).
5. Depends on refresh operations.
6. Z (I) or H (state held), depending on register setting
(BCR1.HIZMEM).
7. Z or O, depending on register setting (STBCR.PHZ).
8. Output when refreshing is set.
9. Operation in respective state when CKIO2ENB = 0
(SH7750/SH7750S) (High-level outputs as
SH7750R).
10. PZ or O, depending on register setting
(FRQCR.CKOEN).
11. Pulled up or not pulled up, depending on register
setting (STBCR.PPU).
12. Pulled up or not pulled up, depending on register
setting (BCR1.IPUP).
13. Pulled up or not pulled up, depending on register
setting (BCR1.OPUP).
14. Pulled up with a built-in pull-up resistance. However
it, cannot use for fixation of an input MD pin at the
time of power-on reset. Pull up or down outside this
LSI.
15. Output when refreshing is set (SH7750R only).
16. Z or O, depending on register setting
(STBCR2.STHZ) (SH7750R only).
17. Z or O, depending on register setting (TOCR,
TCOE)
18. Output state held when used as port.
19. Pulled up or not pulled up, depending on register
setting (BCR1.DPUP) (SH7750R only).
20. Z when CKIO2ENB = 1
21. BGA Package only.
22. Depends on Emulator operations.
Rev.7.00 Oct. 10, 2008 Page xlv of lxxxiv
REJ09B0366-0700