SH7750_08 Datasheet, PDF (635/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Chan-
nel Name
Abbre-
viation
Read/
Area 7
Write Initial Value P4 Address Address
Access
Size
1
DMA source
SAR1
R/W Undefined H'FFA00010 H'1FA00010 32
address register 1
DMA destination DAR1
address register 1
R/W Undefined H'FFA00014 H'1FA00014 32
DMA transfer
count register 1
DMA channel
control register 1
DMATCR1 R/W Undefined H'FFA00018 H'1FA00018 32
CHCR1 R/W^*1 H'00000000 H'FFA0001C H'1FA0001C 32
2
DMA source
SAR2
R/W Undefined H'FFA00020 H'1FA00020 32
address register 2
DMA destination DAR2
address register 2
R/W Undefined H'FFA00024 H'1FA00024 32
DMA transfer
count register 2
DMATCR2 R/W
Undefined H'FFA00028 H'1FA00028 32
DMA channel
CHCR2
control register 2
R/W^*1 H'00000000 H'FFA0002C H'1FA0002C 32
3
DMA source
SAR3
R/W Undefined H'FFA00030 H'1FA00030 32
address register 3
DMA destination DAR3
address register 3
R/W Undefined H'FFA00034 H'1FA00034 32
DMA transfer
count register 3
DMATCR3 R/W
Undefined H'FFA00038 H'1FA00038 32
DMA channel
control register 3
Com- DMA operation
mon register
CHCR3
DMAOR
R/W^*1 H'00000000 H'FFA0003C H'1FA0003C 32
R/W^*1 H'00000000 H'FFA00040 H'1FA00040 32
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
1. Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
2. In the SH7750, writes from the CPU are masked in DDT mode, while writes from
external I/O devices using the DTR format are possible. In the SH7750S, writes from
the CPU and writes from external I/O devices using the DTR format are possible in DDT
mode.
Rev.7.00 Oct. 10, 2008 Page 551 of 1074
REJ09B0366-0700