SH7750_08 Datasheet, PDF (315/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
Section 8 Pipelining
This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor.
Instruction execution is pipelined, and two instructions can be executed in parallel. The execution
cycles depend on the implementation of a processor. Definitions in this section may not be
applicable to SH-4 Series products other than this LSI.
8.1 Pipelines
Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction
fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA),
and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2
shows the instruction execution patterns.
Rev.7.00 Oct. 10, 2008 Page 231 of 1074
REJ09B0366-0700