SH7750_08 Datasheet, PDF (854/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a
BRI interrupt request is generated.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR2.
Table 16.6 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
Description
DMAC
Activation
Interrupt initiated by receive error flag (ER)
Not possible
Interrupt initiated by receive FIFO data full flag Possible
(RDF) or receive data ready flag (DR)
Interrupt initiated by break flag (BRK) or overrun Not possible
error flag (ORER)
Interrupt initiated by transmit FIFO data empty Possible
flag (TDFE)
Priority on
Reset Release
High
Low
See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts.
16.5 Usage Notes
Note the following when using the SCIF.
SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is
set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2)
has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO
control register (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in
SCFTDR2 can be written, allowing efficient continuous transmission.
However, if the number of data bytes written in SCFTDR2 is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE
clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger
number of transmit data bytes.
The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO
data count register (SCFDR2).
SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register (SCFSR2) is
set when the number of receive data bytes in the receive FIFO data register (SCFRDR2) has
become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the
Rev.7.00 Oct. 10, 2008 Page 770 of 1074
REJ09B0366-0700