SH7750_08 Datasheet, PDF (220/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
31
24 23
Address field _{1 1 1 1 0 1 0 1}
31
Data field
14 13
Longword data
Entry
54 210
L
0
Legend:
L: Longword specification bits
: Reserved bits (0 write value, undefined read value)
Figure 4.11 Memory-Mapped OC Data Array
4.6 Memory-Mapped Cache Configuration (SH7750R)
To enable the management of the IC and OC by software, a program running in the privileged
mode is allowed to access their contents.
The contents of IC can be read and written by using MOV instructions in a P2-area program
running in the privileged mode. Operation is not guaranteed for access from a program in some
other area. Any branching to other areas must take place at least 8 instructions after this MOV
instruction.
The contents of IC can be read and written by using MOV instructions in a P1- or P2-area program
running in the privileged mode. Operation is not guaranteed if access is attempted from a program
running in some other area. A branch to the P0, U0, or P3 area must be made at least 8 instructions
after this MOV instruction.
The IC and OC are allocated to the P4 area of the physical memory space. The address and data
arrays of both the IC and OC are only accessible by their data fields. Longword operations must be
used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0
should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750S-
compatible mode, the configuration of the SH7750R's memory-mapped cache is the same as that
of the SH7750 or SH7750S.
Rev.7.00 Oct. 10, 2008 Page 136 of 1074
REJ09B0366-0700