SH7750_08 Datasheet, PDF (795/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes
that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI)
request is generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and
the TxD pin maintains its state.
If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is
generated.
4. After completion of serial transmission, the SCK pin is fixed high.
Figure 15.20 shows an example of SCI operation in transmission.
Rev.7.00 Oct. 10, 2008 Page 711 of 1074
REJ09B0366-0700