SH7750_08 Datasheet, PDF (208/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from
H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-Kbyte RAM area.
Examples of RAM usage with the SH7750R is shown below.
• In SH7750/SH7750S-compatible mode (CCR.EMODE = 0)
H'7C00 0000 to H'7C00 1FFF (8 KB): RAM area (entries 256 to 511)
H'7C00 2000 to H'7C00 3FFF (8 KB): RAM area (entries 256 to 511)
:
:
:
In the same pattern, shadows of the RAM area are created in 8-Kbyte blocks until H'7FFF
FFFF is reached.
• In double-sized cache mode (CCR.EMODE = 1)
In this mode, the 8 Kbytes comprising entries 256 to 511 of OC way 0 are designated as RAM
area 1 and the 8-Kbytes comprising entries 256 to 511 of OC way 1 are designated as RAM
area 2.
H'7C00 0000 to H'7C00 1FFF (8 KB): Corresponds to RAM area 1
H'7C00 2000 to H'7C00 3FFF (8 KB): Corresponds to RAM area 2
H'7C00 4000 to H'7C00 5FFF (8 KB): Corresponds to RAM area 1
H'7C00 6000 to H'7C00 7FFF (8 KB): Corresponds to RAM area 2
:
:
:
In the same pattern, shadows of the RAM area are created in 16-Kbyte blocks until H'7FFF
FFFF is reached.
4.3.7 OC Index Mode
Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective
address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing
is performed using bits [13:5] of the effective address. Using index mode allows the OC to be
handled as two areas by means of effective address bit [25], providing efficient use of the cache.
The SH7750R cannot be used in RAM mode when OC index mode is selected.
Rev.7.00 Oct. 10, 2008 Page 124 of 1074
REJ09B0366-0700