SH7750_08 Datasheet, PDF (199/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least
four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or
U0 area should be located at least eight instructions after the CCR update instruction.
• EMODE: Double-sized cache mode bit
In the SH7750R, this bit indicates whether the double-sized cache mode is used or not.
This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while
the cache is being used.
0: SH7750/SH7750S-compatible mode*¹ (initial value)
1: Double-sized cache mode
• IIX: IC index enable bit
0: Effective address bits [12:5] used for IC entry selection
1: Effective address bits [25] and [11:5] used for IC entry selection
• ICI: IC invalidation bit
When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns
0 when read.
• ICE: IC enable bit
Indicates whether or not the IC is to be used. When address translation is performed, the IC
cannot be used unless the C bit in the page management information is also 1.
0: IC not used
1: IC used
• OIX: OC index enable bit*²
0: Effective address bits [13:5] used for OC entry selection
1: Effective address bits [25] and [12:5] used for OC entry selection
• ORA: OC RAM enable bit*³
When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be
used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.
0: Normal mode (the entire OC is used as a cache)
1: RAM mode (half of the OC is used as a cache and the other half is used as RAM)
• OCI: OC invalidation bit
When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always
returns 0 when read.
Rev.7.00 Oct. 10, 2008 Page 115 of 1074
REJ09B0366-0700