SH7750_08 Datasheet, PDF(77/1162 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7750_08 Datasheet, PDF (77/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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Tables

Section 1 Overview

Table 1.1 LSI Features ........................................................................................................... 1

Table 1.2 Pin Functions.......................................................................................................... 14

Table 1.3 Pin Functions.......................................................................................................... 24

Table 1.4 Pin Functions.......................................................................................................... 32

Table 1.5 Pin Functions.......................................................................................................... 42

Section 2 Programming Model

Table 2.1 Initial Register Values ............................................................................................ 55

Section 3 Memory Management Unit (MMU)

Table 3.1 MMU Registers ...................................................................................................... 74

Section 4 Caches

Table 4.1 Cache Features (SH7750, SH7750S)...................................................................... 111

Table 4.2 Cache Features (SH7750R) .................................................................................... 112

Table 4.3 Features of Store Queues........................................................................................ 112

Table 4.4 Cache Control Registers......................................................................................... 113

Section 5 Exceptions

Table 5.1 Exception-Related Registers .................................................................................. 149

Table 5.2 Exceptions .............................................................................................................. 152

Table 5.3 Types of Reset........................................................................................................ 161

Section 6 Floating-Point Unit (FPU)

Table 6.1 Floating-Point Number Formats and Parameters ................................................... 186

Table 6.2 Floating-Point Ranges ............................................................................................ 187

Table 6.3 Incorrect Operation Result ..................................................................................... 203

Table 6.4 FDIV DRm, DRn (DRn/DRm â DRn) ................................................................ 204

Table 6.5 FADD DRm, DRn (DRn + DRm â DRn) FSUB DRm, DRn

(DRn â DRm â DRn) ........................................................................................... 205

Table 6.6 FMUL DRm, DRn (DRn*DRm â DRn).............................................................. 205

Table 6.7 TRAP Routine Processing...................................................................................... 207

Section 7 Instruction Set

Table 7.1 Addressing Modes and Effective Addresses .......................................................... 211

Table 7.2 Notation Used in Instruction List ........................................................................... 215

Rev.7.00 Oct. 10, 2008 Page lxxvii of lxxxiv

REJ09B0366-0700

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